Harnessing Heterogeneity for Targeted Attacks on 3-D ICs (2024)

As 3-D integrated circuits (ICs) increasingly pervade the microelectronics industry, the integration of heterogeneous components presents a unique challenge from a security perspective. To this end, an attack on a victim die of a multi-tiered heterogeneous 3-D IC is proposed and evaluated. By utilizing on-chip inductive circuits and transistors with low voltage threshold (LVT), a die based on CMOS technology is proposed that includes a sensor to monitor the electromagnetic (EM) emissions from the normal function of a victim die, without requiring physical probing. The adversarial circuit is self-powered through the use of thermocouples that supply the generated current to circuits that sense EM emissions. Therefore, the integration of disparate technologies in a single 3-D circuit allows for a stealthy, wireless, and non-invasive side-channel attack. A thin-film thermo-electric generator (TEG) is developed that produces a 115 mV voltage source, which is amplified 5 × through a voltage booster to provide power to the adversarial circuit. An on-chip inductor is also developed as a component of a sensing array, which detects changes to the magnetic field induced by the computational activity of the victim die. In addition, the challenges associated with detecting and mitigating such attacks are discussed, highlighting the limitations of existing security mechanisms in addressing the multifaceted nature of vulnerabilities due to the heterogeneity of 3-D ICs.

The microelectronics industry is increasingly utilizing three-dimens- ional (3-D) heterogeneous integration as a means to enhance performance, reduce size, provide greater functionality, lower power consumption, and increase the security of integrated circuits (ICs). 3-D ICs allow for increased circuit performance by reducing interconnect length [1]. In addition, the ability to integrate heterogeneous circuits has accelerated research on system level design considerations of 3-D ICs. Specifically, the integration of disparate technologies and process nodes allows for enhanced functionality, including hardware implemented AI algorithms [2]. Node heterogeneity, integrating 45 nm and 5 nm CMOS technology for example, allows for the optimization of different metrics including power, latency, area, and security, within the same package [3]. Functional heterogeneity allows for topologies that might otherwise require separately packaged technologies (i.e. digital circuits, analog circuits, radio frequency (RF) devices, memory, sensors, etc.). A high level representation of the different configurations of a 3-D IC is shown in Fig. 1, where hom*ogeneous and heterogeneous structures are implemented.

When considering security, 3-D integration provides an inherent defense against modern side-channel analysis (SCA) attacks. The use of multi-sourced die for low-cost IC development results in greater challenges for adversaries to extract the functionality of a 3-D stacked IC. However, 3-D circuits are susceptible to side channel attacks due to the high thermal gradients unique to 3-D ICs [4]. In addition, as most companies utilize a fabless model [5], the fabrication and packaging process is completed by third party entities, leaving room for the insertion of malicious circuitry or additional layers by an untrusted foundry or packaging house [6]. Malicious circuitry, or hardware Trojans, allow for a potential leak of sensitive information or a disruption of circuit functionality. Although some research on hom*ogeneous 3-D IC security has been performed [4], the security of advanced 3-D heterogeneous circuits has not been sufficiently explored. By exploiting the inherent heterogeneity of 3-D ICs, attackers have access to a complex design space that contains novel and highly diverse circuits that provide yet unexplored means to breach security mechanisms, compromise system integrity, and extract sensitive information. Such attacks result in severe financial loss, mar the reputation of the designer, and hinder future innovations. Exploring the attack implications of 3-D heterogeneous ICs is, therefore, imperative.

The attack proposed in this paper utilizes the heterogeneity of 3-D ICs as a potential security vulnerability. The adversarial circuit, shown in Fig. 2, is composed of two heterogeneous dies:

• Thermo-electric generator (TEG) - A TEG that leverages the large thermal gradients of a 3-D IC is implemented on the top die of the adversarial circuit. The die is fabricated in a non-CMOS process that includes a silicon substrate, n-type and p-type poly-SiGe as, respectively, negative and positive terminals, and a ceramic layer for facilitating heat flow. The TEG is a non-invasive power harvesting module that utilizes the Seebeck effect to transform a thermal gradient into a supply voltage for the bottom die of the adversarial circuit [7].
  
• On-chip EM probe - A mixed signal CMOS die is integrated that contains a voltage booster, control circuit, and an on-chip inductor used to sense EM emissions from a victim die.
  

The heterogeneous integration of circuits for EM sensing and thermo-electric generation provides a fully wireless and non-invasive attack capable of leaking sensitive information or inducing fault injection on a victim die. The ability to integrate disparate fabrication processes in the same 3-D stack as the victim die(s) allows an attacker to extract secret information by simply placing the adversarial circuit in close proximity to the victim without probing or any physical connections. This paper, therefore, presents a feasibility study of a probeless and connectionless attack.

The paper is organized as follows. Prior work related to heterogeneous security is described in Section 2. The considered threat model for the proposed attack is provided in Section 3. The design of the proposed adversarial circuit is described in Section 4. The utilized circuit models are provided in Section 5. Preliminary data and simulation results are provided in Section 6. Possible countermeasures are described in Section 7, and some concluding remarks are provided in Section 8.

Current security research has focused on the benefits of heterogeneous circuits as a means to mitigate hardware attacks. In [8], a 3-D Heterogeneous System on Chip (HSoC) is proposed that contains a sensor plane as well as separate analog and digital device planes to monitor various phenomenological signals. The objective is to intelligently execute decisions for military applications based on environmental factors that include seismic or acoustic signals. In [9], an architecture is proposed that includes a CMOS-based cryptography unit on one plane and a dynamically reconfigurable resistive RAM (RRAM) on another. The RRAM is designed to function as either the memory for the cryptography unit or a thermal sensor, depending on the state of the cryptographic function. By providing dual functionality, sensitive power signals are masked and the design is more resilient against differential power analysis (DPA) attacks.

Many prior research papers describe the security advantages provided by the split manufacturing of 3-D ICs [10],[11],[12]. Typically, the foundries capable of fabricating more advanced processing nodes are assumed abroad and considered untrusted, while the trusted foundries are assumed on-shore but of older technology. Therefore, front-end of the line (FEOL) logic layers are fabricated in the advanced off-shore processing nodes while the remaining back-end of the line (BEOL) layers are fabricated in the older but secure technology nodes. In addition to FEOL and BEOL split manufacturing, 3-D ICs allow for the fabrication of each stacked die at separate foundries, where a sensitive die is fabricated securely on-shore, while the remaining dies are fabricated off-shore [12]. With such split manufacturing, the true functionality of the circuit is masked to avoid sharing sensitive circuit specifications with an untrusted foundry.

Prior work has demonstrated the security benefits of heterogeneous integration; however, the security vulnerabilities of 3-D ICs have not been adequately explored. Therefore, multiple EM side-channel attacks are discussed in Section 4.2, which can be exploited to attack 3-D ICs. However, none of the current attack strategies have been executed on 3-D ICs, nor have probeless EM attacks been adequately studied.

The capability of integrating disparate technologies in a 3-D IC is available to both trusted and untrusted entities. More research on attack vectors is, therefore, needed to minimize the security vulnerabilities of heterogeneous 3-D ICs. To the best of our knowledge, our proposed circuit is the first non-invasive attack vector that leverages the heterogeneity of a 3-D IC.

The objective of the proposed attack is to covertly extract EM signals emenating from the normal operation of a victim die through on-chip inductors. As compared to other attacks, EM SCA attacks do not require the netlist or information on the process design kit (PDK). However, the physical position and size of the EM probes are primary design considerations to optimally extract sensitive information from a victim IC. Therefore, any information on the placement of victim modules is useful in deciding where to place the adversarial EM sensors. Without physical design information, the attacker must optimize the placement of EM probes to effectively sense across the entire victim IC and extract target signals. Implementing fine-grained EM probes significantly increases the area coverage and spatial accuracy of the attack [13]. However, the time necessary for the attacker to extract meaningful data from the target module increases. The proposed adversarial circuit is designed with fine-grained on-chip inductors in order to prioritize the coverage and spatial accuracy of the EM SCA attack.

Some critical aspects of the threat model include the non-invasive nature of the attack and the low-effort to execute the attack once implemented. Non-invasive attacks are stealthy and less costly as compared to other physical attacks such as reverse engineering or tampering. The ideal attack vector for a malicious user or foundry is one that extracts secret information without the need for probing, depackaging, or the electrical tapping of power ports. EM SCA attacks are generally non-invasive, and the inclusion of the TEG eliminates the need to physically connect to the power supply of the victim IC, which limits detection of the adversarial circuit by monitoring power supply variations [14]. After fabrication, the attack only requires that the two aggressor dies are placed on top of the victim die, without the need for any wired connections between the victim and aggressor circuits. The attack is, therefore, more accessible and stealthier than prior proposed attacks.

The adversarial circuit is implemented as a two-layer, face-to-face bonded (microbumps) 3-D IC. The top layer contains the TEG thermocouples for power generation and the bottom layer includes the on-chip inductors for EM sensing. The theoretical analysis of the TEGs and EM SCA are described in Section 4.1 and 4.2, respectively.

Both the TEG and EM test circuits were analyzed separately. Ansys tools were used for thermal-electric and EM simulations. The TEG is described in Section 5.1, while the developed EM sensor circuit is described in Section 5.2.

5.1 TEG Module

The TEG utilized as the power source for the second adversarial die containing the EM sensors is adapted from [19]. The model of the TEG is developed in Ansys SpaceClaim. The positive and negative terminals, described as legs, are implemented in each thermocouple using n-type and p-type poly-SiGe layers. Aluminum (Al) is used as the hot and cold plates between the poly-SiGe to form junctions. A single thermocouple is shown in Fig. 3. While the substrate is silicon, a ceramic layer is included on top of the hot junctions to increase the thermal gradient between the hot and cold Al plates.

A model of a TEG containing 543 thermocouples is shown in Fig. 4. The ceramic layer is included in Fig. 4a, wheras the ceramic layer is removed in Fig. 4b to depict the interior structure of the TEG. The thermocouples are electrically connected in series but are thermally connected in parallel to enhance current flow. The results of the thermo-electric simulation on the model of the TEG array are described in Section 6. Through simulation of the TEG, the estimate of the generated power supply voltage is used when modeling the amplifier circuit.

5.2 EM Sensor Die

The EM sensor die includes an amplifier to boost the voltage generated by the TEG and an on-chip inductor to sense EM emanations. The amplifier circuit is described in Section 5.2.1, while the on-chip inductor is described in Section 5.2.2.

5.2.1 Amplifier Circuit. The amplifier is implemented on the bottom adversarial die closest to the victim die and utilizes a high swing Colpitts oscillator [17]. A schematic of the voltage boosting circuit is shown in Fig. 5, and the parameters for each component of the voltage booster are listed in Table 1.

Table 1: Parameters of the voltage booster circuit.

VTEG	115 mV
$\boldsymbol {R_{V_{TEG}}}$	5Ω
L1, L2	20 μH
C1	1.2 nF
C2	100 nF
C3 − C8	15 pF
M1(W/L)	200 nm/60 nm
M2 − M7(W/L)	400 nm/60 nm

The DC voltage generated by the TEG is given by V_TEG, while the resistance of the TEG is given by $R_{V_{TEG}}$. The LVT NMOS transistor M₁ oscillates when biased at V_osc. The drain of M₁ is biased to V_TEG, while the gate and source are indirectly applied V_TEG through inductors L₁ and L₂, respectively. A high voltage swing is provided by the resonant LC tank circuit formed by inductor L₁ and capacitors C₁ and C₂. V_osc acts as a starter for the 3-stage voltage multiplier. The circuit provides a 5 × boost of the voltage V_TEG generated by the TEG at the output node V_out.

5.2.2 On-chip Inductor. An on-chip spiral inductor has been modeled in Ansys HFSS as shown in Fig. 7. The spiral inductor is developed in a TSMC 65 nm process, where metal 4 properties are provided to HFSS for characterization of the inductor. The on-chip inductor is used to demonstrate the feasibility of chip-to-chip EM snooping. Current flow in a victim circuit is emulated by a wire placed under a 160 μm by 160 μm inductor at a distance of 215 μm.

Ansys Mechanical and HFSS were used to simulate the TEG and inductor, respectively, while Cadence Virtuoso was used to analyze the amplifier circuit. The TEG simulation is described in Section 6.1, while the simulation of the on-chip inductor is described in Section 6.2.

6.1 TEG Simulation

The thermal and electrical conductivity for each material, as well as the Seebeck Coefficients for the positive and negative legs within a thermocouple, are used to calculate the voltage generated by the TEG. The material properties of the n-type and p-type poly-SiGe are listed in Table 2 [19]. In order to generate current, a temperature gradient was applied across the two layers of the TEG. The ceramic is set to 50°C while the substrate is set to 40°C. The resulting temperature profile of the TEG die determined by simulation using Ansys Mechanical is shown in Fig. 6a, where high temperatures (50°C) are depicted in red and low temperatures (40°C) are depicted in blue.

Table 2: Material properties of poly-SiGe in simulation of TEG [19].

poly-SiGe	S (μV/K)	σ (mΩcm)	k (W/m/K)
n-type	− 190	1.1	3.5
p-type	35	6.2	3.5

A steady-state thermo-electric analysis is performed in Ansys Workbench to characterize the voltage generated by the TEG. For the simulation, a ground node must be set at one end of the thermocouple chain. The resulting voltage generated by the TEG is shown in Fig. 6b . Beginning with the ground terminal (dark blue cells in Fig. 6b), an imbalance of charge across the thermocouple chain results from the movement of charge carriers due to the temperature difference between plates of the thermocoupled layers, which generates an electromotive force that increases with each thermocouple added in series. The voltage provided by the TEG is taken from the final thermocouple of the chain (dark red cells in Fig. 6b), which is approximately 115 mV for the current configuration of the TEG array.

The generated voltage is directly dependant on the magnitude of the temperature gradient and the number of thermocouples added in series. Since there is minimal control over the temperature gradient in real time use of the 3-D IC, adjusting the number of thermocouples is a design variable that is optimized to generate a target output voltage. Providing 115 mV as the input voltage to the amplifier circuit yields a final voltage V_out of 575 mV when amplified by 5 ×.

6.2 Analysis of On-chip Inductor

A 1.7 mA average current with peak to peak current pulses of 0.35 mA is induced on the on-chip sensor, which is biased by a V_out voltage of 575 mV provided by the amplifier. The current is induced by a 1.2 V, 1 GHz square wave signal propagating along a wire of 170 μm length that draws 1.8 mA of current on the victim die. The results from simulation of the inductor-based sensor and an active wire emulating current flow on the victim IC are shown in Fig. 7. The effects of the induced magnetic field are sensed by the on-chip inductor, which results in an induced current that is monitored for side-channel information. To analyze the effect of relative probe position on the induced EM field, the active wire is placed off-center from the probe, as shown in Fig. 7b . The resulting magnetic field is weaker, but sufficient to induce a current in the on-chip inductor. The induced current fluctuates in response to the switching activity of the wire.

Since excitations are only presented in a single wire, the magnitude of the magnetic field is small. Sensitive circuits, including AES and DES modules, include a large number of switching paths, which results in higher induced magnetic fields sensed by the on-chip inductors. Although the magnetic field is stronger, the induced signal requires amplification. Therefore, an integrated wideband low noise amplifier (LNA) is needed to boost the monitored side-channel signal.

Preventing an attack that utilizes self-powered and non-invasive integrated sensors requires careful consideration. Incorporating EM shielding reduces the emissions from the victim die and, therefore, limits the effectiveness of the on-chip inductor sensors. In [25], an on-chip spiral inductor is utilized to mask the EM emissions from a victim IC. A sensing inductor is described in [26], which detects EM SCA attacks when the magnetic field surrounding the inductor is disturbed by the presence of an external EM probe. Another method that counters EM side-channel attacks utilizes additional circuitry that suppresses EM emissions. STELLAR, described in [27], mitigates EM attacks by 1) routing sensitive circuitry in the lower-level metals of the victim IC and 2) embedding the sensitive circuits within a signature attenuation hardware (SAH) unit that suppresses vulnerable current signatures that propagate through higher metal layers of the victim IC. Similarly, countermeasures have been developed to suppress voltage noise on the power distribution network (PDN) [28]. The voltage noise on the PDN is utilized in an EM attack to aid the attacker in understanding when the circuit is switching. However, adding decoupling capacitors near noisy PDN nodes reduces fluctuations in current, which minimizes the risk of EM SCA attacks on the victim IC.

In this paper, a non-invasive attack is proposed that utilizes the heterogeneity of a 3-D IC. Non-invasive attacks are stealthier and less costly as compared to physical attacks such as reverse engineering or tampering. Therefore, a self-powered circuit that leverages heterogeneous technologies is developed to non-invasively attack an unexpecting victim die. The proposed attack scenario includes a victim die in close proximity to a device plane with thermocouples that generates power and a plane with on-chip inductors to sense EM emanations from a victim IC.

The proposed TEG array includes 543 thermocouples and produces an output voltage of 115 mV. The amplifier circuit is capable of boosting the final supply voltage by 5 ×. An on-chip inductor that senses the EM emanations of a circuit is simulated to demonstrate the feasibility of the non-invasive attack. In addition, the challenges associated with detecting and mitigating non-invasive and self-powered attacks is discussed, which analyzes the limitations of existing security measures in addressing the multifaceted nature of threats stemming from 3-D IC heterogeneity.

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